![]() ![]() Packets_in : in commads_array_t(0 to 17)(63 downto 0) Type commands_array_t is array (natural range ) of std_logic_vector ![]() In vhdl 2008, it is legal to a declare array types of an unconstrained array type, and then declare the length when you create the signal/variable. because the commands_array type (usual convention is to pre/post pend type names with _t or _type to avoid confusion with signals/variables etc) already has 64 bit slv's declared, there is no need to declare the size of them. Commands_array, is a 1D array, but you're trying to declare packets_in as a 2D array. I still have some problems in my design and getting to simulate it would help a lot.ġ. Is there anything I can do about that?Įdit: I deleted the first question because I succeeded (almost). Even when my code worked (though not in the way I wanted) I saw that my outputs, the array's cells, are correct, so the problem is not with the arrays. I'm trying to use SignalTap to view the arrays but they are always 0. Packets_in : IN commands_array(0 TO 17, 63 DOWNTO 0) Ģ. Too many indices (2) for array type work.my_mands_array (dimensionality 1). I'm also trying to simulate this using Modelsim, but am getting the following error: In one of the modules the array port is this:ġ. The same type of array is an output of one module and an input of another. ![]() Type commands_array is array (natural range ) of std_logic_vector(63 downto 0) I have two problems with a 1-d array I'm using. ![]()
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